1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a bit registering layer for recording information on whether memory cells storing data are in a good state or a bad state.
2. Discussion of Related Art
In a semiconductor memory device, if even one cell is found to be defective, the semiconductor memory device cannot perform its function normally and it is treated as defective. Even though the probability that defects occur is low, defective memory cells do occur and decrease yield. The defective cell may, however, be replaced with an auxiliary memory cell, which is prepared in advance inside a semiconductor memory device, so as to increase the yield. Because of this, a redundancy circuit is provided in order to repair the defective cell, which may be generated during the fabrication of semiconductor memory devices.
However, when the redundancy circuit is used, an area of a chip is increased and the number of tests necessary to repair defects is increased. Accordingly, the redundancy circuit has not been used much in a large scale integrated circuit (LSI). The redundancy circuit has been employed in a dynamic random access memory (DRAM) from 64K through 256K since the chip area increases compared to that of a LSI device.
More specifically, the redundancy circuit of the semiconductor memory device is a circuit used to fabricate defect-free semiconductor memory devices by: further forming additional cells (for example, (n+m)×(n+m′)−n×n) in addition to the cells of a semiconductor memory device (for example, n×n cells) (here, m and m′ mean the numbers of the redundancy cells); analyzing whether a defective memory cell exists or no; disconnecting a row or column including one or more defective cells; and connecting to the redundancy cells, to thereby provide n×n cells.
An efficiency of such a redundancy circuit will be explained in reference to attached drawings.
FIGS. 1 through 3 illustrate yields of an n×n memory block in accordance with a generation rate of defective bits for various redundancy cell sizes.
In FIG. 1, a Y-axis indicates a yield of memory blocks, and an X-axis indicates a generation rate of defective bits. The curves in FIG. 1 illustrate a relation of a generation rate of defective bits and a yield of 16×16 memory blocks in accordance with a redundancy cell size (m;m=1,2,4.) corresponding to the memory block.
As shown, the yield of memory blocks increases as the number of redundancy cells is increased at a constant generation rate of defective bits. For example, when a generation rate of defective bits is 0.01 (1%), and the number of redundancy cells m is 1, a yield of memory blocks is about 0.6 (60%). In a same generation rate of defective bits, when the redundancy cell size m is 2, a yield of memory blocks is about 0.95 (95%). That is, when a generation rate of defective bits is 0.01 and a redundancy cell size m is 4 or more, the yield of memory blocks is 1.
The description of the graphs of FIGS. 2 and 3 is similar to the description of FIG. 1.
As shown in FIG. 3, in order to fabricate a memory block of n×n=1024×1024, even though a redundancy cell size is 2048×2048, that is, a semiconductor memory device is fabricated with a size of nine times the desired size of the memory device to be fabricated, a yield of a memory block is 0 at about a 0.3% generation rate of defective bits or higher.
That is, in a nanometer-scale memory device (for example, molecular memory, carbon nano-tube memory, atomic memory, single electron memory, and particularly, a memory fabricated by a chemical bottom-up method), in which a generation rate of defective bits will be difficult to decrease down to several percent or lower (for example, 1%), the method of repairing defective cells using redundancy cells as above may not be useful
The nanometer-scale memory device is a memory device fabricated using a nano technology such as a submicron technology capable of controlling in units of nanometer (e.g., level to directly control molecules), that is, 0.000000001 meter. The nanometer-scale memory device may be called a nano device or a nano memory device. Examples of nanometer-scale memory devices are disclosed in U.S. Pat. NOS. 6,936,233 and 6,750,471.
A method of forming a separate memory layer and recording information on defective memory cells in the memory layer similar to a structure of a file allocation table (FAT) of a hard disk driver may be employed in order to overcome defects of the memory designing method of repairing defective cells using redundant cells. However, this method may also cause problems in the yield of memory blocks in accordance with a size of a block as illustrated in FIG. 4.
FIG. 4 is a graph illustrating an example of a yield of memory blocks when an n×n size of a semiconductor memory device is treated as a block unit. As illustrated in FIG. 4, as a size of a block is increased, a yield of memory blocks is rapidly decreased. For example, when a size of a memory block is 16×16 (n=16), and a generation rate of defective bits is 5E-3 (0.5%), a yield of memory blocks does not reach 0.4 (40%). This means that an area of the memory block is two times greater than if no defective bits occurred, and if the block size is further increased, this causes a problem that a required area is rapidly increased.